搜索资源列表
HASH
- hash加速器的verilog实现，也用于fpga或asic-hash verilog rtl
AES
- aes源码verilog带有仿真环境，可用于FPGA实现-aes verilog rtl
antenna-effect
- 硬件电路设计中消除天线效应的电路RTL级Verilog代码-RTL grade of Verilog codes for reducing antenna effect
spi_rtl
- 支持主从模式的、可综合的SPI verilog代码-Supports master and slave mode SPI communication module can be integrated RTL code
gsm_ddc
- 基于GSM的数字下变频代码，能够直接生成Verilog代码，需要Synplify DSP 支持。-GSM DDC code. This Model can directly generate RTL code via Synplify DSP.
BPSK_receiver
- BPSK接收机设计，能够通过Synplify DSP直接生成Verilog代码。-BPSK Reciver model. This simulink model can generate RTL code via Synplify DSP.
dct2d
- 2D-DCT, 二维离散余弦变换模型。能够通过Synplify DSP生成Verilog代码 -2D-DCT model. This simulink model can generate RTL code via Synplify DSP.
pipe_mul
- 移位加乘法器的实现；移位加乘法器的流水线结构的实现。代码清晰明了。-multiply verilog RTL；pipelin multiply verilog RTL；good coding stytle
ss_pcm.tar
- PCM Verilog RTL Reference Code
hdb3_v3
- Quartus环境下使用Verilog编写的串口程序，RTL和时序仿真已过-Quartus under the environment of a serial procedures written in Verilog, RTL and timing simulation has be passed
uart_v1.1
- Quartus下开发Verilog编写的串口程序，主要包含串并互转模块等，通过RTL和时序仿真-Quartus under the environment of a serial procedures written in Verilog, contains the Conversion module and so on RTL and timing simulation has passed
iic
- 通过verilog语言实现了关于IIC协议，并且通过了modelsim的功能仿真验证以及板卡之间的RTL调试。-the verilog code about IIC standard，checked by modelsim，and make ture the IIC function in RTL。
t51.tar
- MCU 8051 Verilog RTL Code
uart16550.tar
- UART Verilog RTL Code
2_digital_clock
- 采用Verilog HDL RTL 描述完成数字钟，基于basys3，软件平台：vivado-Using Verilog HDL RTL to complete the descr iption of digital clock based on basys3 software platform: vivado
RS485_Revc
- rs485 receive end verilog rtl code
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
i2c_testbench
- i2c verilog rtl with testbench very good code and works perfectly with cadence ius and ncverilog
usb
- verilog rtl code for usb controller.
lab1 Vivado Design Flow
- 适用于对verilog语言的初步学习，本文本就对RTL的编写，功能仿真，实现，布线，综合，以及生成比特流等环节进行了初步的描述。适合初学者学习。(For the preliminary study of Verilog language)